In a semiconductor integrated circuit device (Large Scale Integration: LSI) with multiple power supplies, a level shift circuit is provided to couple between circuits with different power supply voltages (refer to WO 2007/135799).
The level shift circuit is used for a digital-to-analog conversion circuit (DAC circuit) 10 illustrated in FIG. 1, for example. The DAC circuit 10 outputs an output current Io in accordance with a multiple-bit input signal DT.
The DAC circuit 10 includes flip-flop circuits 11. The flip-flop circuits 11 are provided in the number corresponding to the number of bits of the input signal DT. The flip-flop circuits 11 synchronize with a clock signal CK to latch the corresponding bit of the input signal DT, and output a signal at a level in accordance with the latched level. Conversion circuits (decoders) 12 decode output signals of the flip-flop circuits 11 to output the decoded signals. A first high potential voltage VDD in accordance with the level of the input signal DT is supplied to the flip-flop circuits 11 and the conversion circuits 12.
Level shift circuits 13 are supplied with the first high potential voltage VDD and a second high potential voltage AVD different therefrom. The second high potential voltage AVD is a voltage supplied to obtain the output current Io and is a voltage higher than the first high potential voltage VDD. The level shift circuits 13 are provided in the number corresponding to the number of bits of the output signals of the conversion circuits 12. Each of the level shift circuits 13 converts the level of a corresponding one-bit signal from the level of the first high potential voltage VDD to the level of the second high potential voltage AVD. Therefore, each level shift circuit 13 converts the level of the signal output from the corresponding conversion circuit 12 to a level in accordance with the second high potential voltage AVD to output the converted signal.
A level shift circuit 14 is supplied with the second high potential voltage AVD. The level shift circuit 14 converts the level of the clock signal CK from the level of the first high potential voltage VDD to the level of the second high potential voltage AVD to output a converted clock signal ACK.
Flip-flop circuits 15 are provided in the number corresponding to the number of bits of the output signals of the level shift circuits 13. Each flip-flop circuit 15 is formed by transistors having a high withstanding voltage characteristic to operate at the second high potential voltage AVD. Each flip-flop circuit 15 synchronizes with the clock signal ACK output from the level shift circuit 14 to latch the output signal of the corresponding level shift circuit 13, and outputs a signal in accordance with the latched level. The input timing of a bit into each flip-flop circuit 15 depends on a delay in a signal path through the conversion circuit 12 and the level shift circuit 13. The flip-flop circuits 15 are provided to cause the timings of bits varying due to differential delays between the signal paths to conform to each other.
Driver circuits 16 operate at the second high potential voltage AVD, and generate driving signals in accordance with the output signals of the flip-flop circuits 15. A current conversion circuit (expressed as “current DAC”) 17 includes a plurality of current sources and drives these current sources in accordance with the driving signals. The current conversion circuit 17 then combines currents of the current sources to generate the output current Io.
The DAC circuit 10 as in the above includes a plurality of flip-flop circuits formed by transistors having a high withstanding voltage characteristic. A transistor having a high withstanding voltage characteristic requires a large footprint. Therefore, the level shift circuit occupies a large area and brings an increase in the area of a semiconductor integrated circuit.